1. Field of the Invention
The present invention relates to a push-pull type power supply device suitable for a high-speed memory device and electronic equipment which comprises this power supply device and uses the output thereof for the power supply for termination.
2. Description of the Related Art
Recently the development of memory devices in attempts to further increase data transfer speed is actively on-going as the performance of electronic equipment progresses. Of this equipment, a DDR (Double Data Rate) synchronous DRAM (DDR-SDRAM) has been commercialized, which synchronizes data transfer for both edges, rise and fall, of a clock signal, to increase the data transfer speed of a synchronous DRAM (SDRAM), which operates synchronizing clock signals.
In a DDR-SDRAM, a high-speed interface with small amplitude signals using the power supply voltage for termination and reference voltage, is used for the high-speed data transfer (e.g. Japanese Patent Application Laid-Open No. 2001-195884). FIG. 3 is a partial circuit diagram of an electronic equipment depicting a configuration of this interface. The electronic equipment 49 comprises a controller 51, which is, for example, a microcomputer, DDR-SDRAM 52, and the power supply device for termination 50 for outputting the power supply voltage for termination (VTT). The controller 51 and the DDR-SDRAM 52 are connected by a signal line via a resistor for interface 53, and this signal line and the power supply for termination (VTT) of the power supply device for termination 50 are connected via a resistor for interface 54 at the connection point Ni of the resistor for interface 53 at the DDR-SDRAM 52 side.
In this example, the system power supplies (VDD) of the controller 51 and the DDR-SDRAM 52 are both set to 2.5V, and the power supply voltage for termination (VTT) and the reference voltage (VREF) are both set to 1.25V, and the resistance values of the resistors for interface 53 and 54 are also equalized. The controller 51, of which the output circuit 61 is constructed in a CMOS configuration, outputs 2.5V as high level and 0V as low level. These high and low level voltages are divided by the resistors for interface 53 and 54, and decrease their amplitude to be 1.875V and 0.625V respectively at the connection point N1. These signals with lower amplitude are input to the non-inversion input terminal of the input signal differential amplifier 62 of the DDR-SDRAM 52, and high level/low level is judged at high-speed by comparing with the 1.25V of the reference voltage (VREF) to be input to the inversion input terminal.
In order to implement such a fast interface with small amplitude, the power supply device for termination 50 for outputting the power supply voltage for termination (VTT) and the reference voltage (VREF) are necessary. For the power supply device for termination 50, the power supply device disclosed in Japanese Patent Application No. 2003-307710 is proposed by the present inventor. FIG. 4 shows this power supply device, but in this diagram, the portion related to the offset, which is not directly related to the present invention, is omitted.
This power supply device 101, which is the so called push-pull type, outputs the power supply voltage for termination (VTT) from the power supply voltage output terminal for termination (VTT output terminal) and the reference voltage (VREF) from the reference voltage output terminal (VREF output terminal), and is comprised of a reference voltage generation circuit 106 for generating reference voltage (VREF), a transistor for feeding 111 disposed between the input power supply (VTT_IN) and the VTT output terminal, a transistor for discharging 112 disposed between the ground potential and the VTT output terminal, and the differential amplification circuits 113 and 114 to which the power supply voltage for termination (VTT) is fed back, controlling the transistors for feeding and discharging 111 and 112 respectively by comparing VTT with the reference voltage (VREF). Therefore the differential amplification circuit 113 and the transistor for feeding 111 form a first feedback loop, and the differential amplification circuit 114 and the transistor for discharging 112 form a second feedback loop. A stabilization capacitor 119, for stabilizing the power supply voltage for termination (VTT), is connected to the VTT output terminal.
The reference voltage generation circuit 106 is comprised of resistors 117 and 118 for dividing the voltage of the input power supply (VDDQ) to generate the reference voltage (VREF), and a buffer amplifier 115 for outputting this reference voltage (VREF). The resistors 117 and 118 have equal resistance values. The reference voltage (VREF) is output to the outside from the reference voltage output terminal (VREF output terminal), and also is output to the differential amplification circuits 113 and 114.
In this power supply device 101, the input power supply (VCC) of the differential amplification circuits 113 and 114 and the buffer amplifier 115 are set to 5V, and the input power supply (VTT_IN) of the transistor for feeding 111 and the input power supply (VDDQ) of the resistors 117 and 118 are set to 2.5V, the same as the above mentioned system power supply (VDD) in FIG. 3, by decreasing the voltage from the input power supply (VCC) by a regulator (not illustrated). Therefore the reference voltage (VREF), which is generated by dividing the 2.5V voltage of the input power supply (VDDQ) by the resistors 117 and 118, becomes 1.25V. The above mentioned first and second feedback loops function so as to match the power supply voltage for termination (VTT) to this reference voltage (VREF) 1.25V.